Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data. However, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.
To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In an SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency. A general overview of software and hardware for SIMT architectures can be found in Shane Cook, CUDA Programming Chapter 3, pages 37-51 (2013).
A graphics processor typically includes a thread scheduler to dispatch the threads to one of several multiprocessors within the processor. Thus, the thread scheduler attempts to load threads per multiprocessor to determine whether to dispatch threads to a particular multiprocessor in order to load-balance the threads across the multiprocessors. However, this can lead to excessive cross-multiprocessor synchronization overhead for thread groups that heavily use barrier synchronization, which ultimately results in reduced performance.